Upcoming Research Presentation
High-Resolution TDC Architectures on FPGAs
Presenter: Ikram Ait Talhiq, Ph.D. Candidate, Erasmus+ Program, Secure and Mixed Architecture for Reliable Technologies and Systems (SMARTS), INPT
We are pleased to invite you to an upcoming presentation covering the investigation and implementation of high-resolution Time-to-Digital Converter (TDC) architectures for on-chip timing measurement.
This session will explore a comprehensive evaluation of various TDC designs to identify the optimal balance between hardware complexity, timing resolution, and robustness against PVT variations. Attendees will also learn about the experimental characterization and practical implementation of the most suitable architecture on a state-of-the-art FPGA platform.
